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Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs

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8 Author(s)
Kuo-Nan Yang ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Huan-Tsung Huang ; Ming-Jer Chen ; Yeou-Ming Lin
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This paper examines the edge direct tunneling (EDT) of holes from p+ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness TOX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field EOX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates EOX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once EOX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected

Published in:

IEEE Transactions on Electron Devices  (Volume:48 ,  Issue: 12 )