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DC pulse hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs

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3 Author(s)
Ja-Hao Chen ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Shyh-Chyi Wong ; Yeong-Her Wang

The DC pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in nMOSFETs in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate DC pulse stress parameters in GIDL which include frequency, rise/fall time, and stressing pulse amplitude. The contributions of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC pulse hot-carrier-stress reliability analysis under circuit operation

Published in:

IEEE Transactions on Electron Devices  (Volume:48 ,  Issue: 12 )