A fast multi-resolution block matching algorithm and its LSI architecture for low bit-rate video coding

We propose a fast multi-resolution block-matching algorithm (BMA) using multiple motion vector (MV) candidates and spatial correlation in MV fields, called a multi-resolution motion search algorithm (MRMCS). The proposed MRMCS satisfies high estimation performance and efficient LSI implementation. This paper describes the MRMCS with three resolution levels. At the coarsest level, two MV candidates are obtained on the basis of minimum matching error for the next search level. At the middle level, the two candidates selected at the coarsest level and the other one based on spatial MV correlation at the finest level are used as center points for local searches, and a MV candidate is chosen for the next search level. Then, at the finest level, the final MV is obtained from local search around the single candidate obtained at the middle level. This paper also describes an efficient LSI architecture based on the proposed algorithm for low bit-rate video coding. Since this architecture requires a small number of processing elements (PEs) and a small size on-chip memory, MRMCS can be implemented with a much smaller number of gates than other conventional architectures for full-search BMA while keeping a negligible degradation of coding performance. Moreover, the proposed motion estimator can support an advanced prediction mode (8/spl times/8 prediction mode) for H.263 and MPEG-4 video encoding. We implement this architecture with about 25 K gates and 288 bytes of RAM for a search range of [-16.0, +15.5] by using a synthesizable VHDL.