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Low-power high-performance arithmetic circuits and architectures

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2 Author(s)
Fahim, A.M. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Elmasry, M.I.

A new class of dynamic differential logic families, swing limited logic (SLL), is proposed for low-power high-performance applications. Two implementations of SLL, short-circuit current logic (SC2L) and clock-pulse controlled logic (CPCL), are designed. Low power is achieved by aggressively reducing logic swing. Using a 0.35-μm CMOS technology and a nominal supply voltage of 3.3 V, an SC 2L 8-bit carry ripple adder (CRA) is implemented. It offers an order of magnitude less energy-delay product than several other logic families. Furthermore, two multipliers are constructed to demonstrate how SLL can be used in large circuit applications

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 1 )