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A 0.5-μm very-high-speed silicon bipolar devices technology U-groove-isolated SICOS

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5 Author(s)
T. Shiba ; Hitachi Ltd., Tokyo, Japan ; Y. Tamaki ; T. Kure ; T. Kobayashi
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A 0.5-μm high-performance silicon bipolar technology is developed and a very-high-speed emitter-coupled-logic (ECL) circuit is demonstrated. Circuits are fabricated with a 0.5-μm SICOS (sidewall base contact structure) technology featuring U-groove isolation, a shallow impurity profile, and reduced base resistance. A U-groove-isolated SICOS structure is realized by the new self-alignment technology using the double polysilicon planarization method. To reduce the extrinsic base resistance, a large-grain base polysilicon is grown from the amorphous silicon layer. A greatly reduced substrate capacitance and small base resistance are obtained. Using these technologies, a minimum ECL gate delay of 27 ps at Fin =1 is realized. A 20-ps ECL gate will be possible in a device having a smaller emitter and the optimal graft base depth

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IEEE Transactions on Electron Devices  (Volume:38 ,  Issue: 11 )