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A new cell structure with a spread source/drain (SSD) MOSFET and a cylindrical capacitor for 64-Mb DRAM's

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8 Author(s)
Yamada, T. ; Toshiba Corp., Kawasaki, Japan ; Samata, S. ; Takato, H. ; Matsushita, Y.
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A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs

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Electron Devices, IEEE Transactions on  (Volume:38 ,  Issue: 11 )