By Topic

An iterative calculation method of the neuron model for hardware implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
N. Chujo ; Toyota Central R&D Labs. Inc., Aichi, Japan ; S. Kuroyanagi ; S. Doki ; S. Okuma

Artificial neural networks (ANN) have the potential of parallel processing by the integrated circuit technology. Recently, over one million gates are available by the latest field programmable gate array (FPGA). However, the sum-of-product circuit used for evaluating the inputs of a neuron model is complex and not effective for hardware implementation by FPGAs. In this paper, an improved calculation algorithm of the perceptron-type neuron model is proposed, which is based on the multidimensional binary search. Since the search does not need the sum-of-product circuit, the designed neuron circuit is small and fast and is suitable for hardware implementation

Published in:

Industrial Electronics Society, 2000. IECON 2000. 26th Annual Confjerence of the IEEE  (Volume:1 )

Date of Conference:

2000