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Experience with term level modeling and verification of the M*CORE TM microprocessor core

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3 Author(s)
Lahiri, S. ; Carnegie Mellon Univ., Pittsburgh, PA, USA ; Pixley, C. ; Albin, K.

The paper describes the use of term-level modeling and verification of an industrial microprocessor, M*CORETM which is a limited dual-issue, super-scalar processor with instruction prefetching mechanism, deep pipeline, multicycle functional units, speculation and interlocks. Term-level modeling uses terms, uninterpreted functions and predicates to abstract the data path complexity of the microprocessor. The verification of the control path is carried out almost mechanically with the aid of CMU-EVC, an extremely efficient decision procedure based on the Logic of Positive Equality with Uninterpreted Functions (PEUF). The verification effort resulted in detection of a couple of non-trivial bugs in the microarchitecture in design exploration phase of the design. The paper demonstrates the effectiveness of CMU-EVC for automated verification of real-life microprocessor designs and also points out some of the challenges and the future work that need to be addressed in term-level modeling and verification of microprocessors using CMU-EVC

Published in:

High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International

Date of Conference:

2001

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