By Topic

Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
4 Author(s)
Sungjoo Yoo ; SLS Group, TIMA Lab., Grenoble, France ; Nicolescu, G. ; Gauthier, L. ; Jerraya, A.A.

To fast evaluate HW/SW implementation of multiprocessor SoC communication, we present a method to simulate operating systems (OSs) on a simulation host without running instruction set simulators and generic OS simulation models. The method enables fast timed OS simulation including the preemption of task execution. Together with the fast simulation of synthesizable HW code (e.g. in synthesizable C), it will enable fast evaluation of HW/SW implementation of multiprocessor SoC communication

Published in:

High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International

Date of Conference: