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Taylor expansion diagrams: a new representation for RTL verification

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4 Author(s)
Ciesielski, M. ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; Kalla, P. ; Zhihong Zeng ; Rouzeyre, B.

A new, compact, canonical representation for arithmetic expressions, called Taylor expansion diagram, is presented. This representation is based on a non-binary decomposition principle. It treats the expression as a continuous, differentiable function and applies Taylor series expansion recursively over its symbolic variables. The resulting Taylor expansion diagram (TED) is canonical for a fixed variable order. We present a theory of TED, and show how to obtain a reduced, normalized representation. We demonstrate that it has linear space complexity for arbitrarily complex polynomials, while time complexity to generate the representation is comparable to that of *BMD. The proposed TED representation is intended to facilitate the verification of RTL specifications and hard. ware implementations of arithmetic designs, and especially the equivalence checking of complex arithmetic expressions that arise in symbolic verification

Published in:

High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International

Date of Conference:

2001