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A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery

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3 Author(s)
Yongsam Moon ; Inter-University Semicond. Res. Center, Seoul Nat. Univ., South Korea ; Deog-Kyoon Jeong ; Gijung Ahn

For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3 × oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and intersymbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25-μm CMOS technology, operates at 2.5 GBaud over a 10-m 150-Ω STP cable and at 1.25 GBaud over a 25-m cable with a bit error rate (BER) of less than 10-13

Published in:

IEEE Journal of Solid-State Circuits  (Volume:36 ,  Issue: 12 )