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Compact low voltage four quadrant CMOS current multiplier

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4 Author(s)
Ravindran, A. ; Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA ; Ramarao, K. ; Vidal, E. ; Ismail, M.

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz

Published in:

Electronics Letters  (Volume:37 ,  Issue: 24 )

Date of Publication:

22 Nov 2001

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