By Topic

Area and power reduction of embedded DSP systems using instruction compression and re-configurable encoding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
S. G. Chandar ; Texas Instruments India Ltd., Bangalore, India ; M. Mehendale ; R. Govindarajan

Proposes a run-time reconfiguration mechanism to map multiple instructions on a single compressed bit pattern, thus enabling significant code compression. This results in reduced area due to smaller program memory size and also reduces instruction fetch related power dissipation. We enhance Texas Instruments DSP core TMS320C27x to incorporate this mechanism and evaluate the improvements on code size and instruction fetch energy using real life embedded control application programs. We show that with minimal hardware overhead, we can reduce code size by over 10% and instruction fetch energy by over 40%.

Published in:

Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on

Date of Conference:

4-8 Nov. 2001