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The design and optimization of SOC test solutions

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3 Author(s)
Larsson, E. ; Dept. of Comput. Sci., Linkoping Univ., Sweden ; Peng, Z. ; Carlsson, G.

We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.

Published in:

Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on

Date of Conference:

4-8 Nov. 2001