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Power-delay modeling of dynamic CMOS gates for circuit optimization

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2 Author(s)
J. L. Rossello ; Phys. Dept., Balearic Islands Univ., Palma de Mallorca, Spain ; J. Segura

We present an accurate analytical expression to compute power and delay of domino CMOS circuits from a detailed description of internal capacitor switching and discharging currents. The expression obtained accounts for the main effects in complex sub-micron gates like velocity saturation effects, body effect, device sizes and coupling capacitors. The energy-delay product is also evaluated and analyzed. Results are compared to HSPICE simulations (level 50) for a 0.18 /spl mu/m CMOS technology.

Published in:

Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on

Date of Conference:

4-8 Nov. 2001