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Efficient test cost reduction procedure for parallel-serial scan circuits

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1 Author(s)
J. M. Solana ; Dept. de Electron. y Comput., Cantabria Univ., Santander, Spain

An efficient test generation procedure aimed at reducing test application cost in parallel-serial scan (PASE-scan) circuits is presented. The procedure is based on the structure and configuration of this type of full-scan circuits. The results obtained with a set of ISCAS89 benchmark circuits are provided, showing the effectiveness of this technique as regards test clock reduction

Published in:

Electronics Letters  (Volume:37 ,  Issue: 21 )