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Design and performance evaluation of PentiumR III microprocessor packaging

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4 Author(s)
Sarangi, A. ; Intel Corp., Hillsboro, OR, USA ; Gang Ji ; Arabi, T. ; Taylor, G.F.

This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest PentiumR III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 μm and the previous 0.18 μm silicon package technology designed for compatibility with existing systems

Published in:
Electrical Performance of Electronic Packaging, 2001

Date of Conference: 2001

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