By Topic

Analysis of static and dynamic behaviour of SiC and Si devices connected in cascode configuration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
A. Mihaila ; Dept. of Eng., Cambridge Univ., UK ; F. Udrea ; R. Azar ; G. Brezeanu

This paper presents an analysis of the static and dynamic behaviour of a 1.2 kV SiC vertical JFET. The JFET can block voltages up to 1450 V (for VGS=80 V), with a specific on-resistance as low as 2.3 mΩcm2. The mixed-mode performance is investigated by coupling the SiC JFET in a cascode circuit with a low power Si MOSFET. Comparing the circuit performance to that of a SiC trench MOSFET, it turns out that the SiC/Si cascode is almost twice faster than the MOSFET. Coupling this with the fact that the SiC/Si cascode pair has better on-state performance, it is concluded that the cascode is a superior alternative to the classical SiC trench MOSFET

Published in:

Semiconductor Conference, 2001. CAS 2001 Proceedings. International  (Volume:2 )

Date of Conference:

Oct 2001