Referenced Items are not available for this document.
The design plan and measurement results of a very high speed 6-bit CMOS Flash Analog-to-digital converter (ADC) are presented. The very high acquisition speed is obtained by improved comparator design and optimized pre-amplifier design. At these high frequencies power-efficient error correction logic is necessary. Measurements show the high conversion speed of the ADC. Maximum acquisition speed is above 1 GHz.
Published in:
Microwave Symposium Digest, 2001 IEEE MTT-S International
(Volume:3
)
Date of Conference: 20-24 May 2001
- Page(s):
- 2131 - 2134 vol.3
- Meeting Date :
- 20 May 2001-25 May 2001
- ISSN :
- 0149-645X
- Print ISBN:
- 0-7803-6538-0
- INSPEC Accession Number:
- 7036579
- Conference Location :
- Phoenix, AZ, USA
- Digital Object Identifier :
- 10.1109/MWSYM.2001.967335
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
