By Topic

Design of a totally self checking signature analysis checker for finite state machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Ottavi, M. ; Dept. of Electron. Eng., Rome Univ., Italy ; Cardarilli, G.C. ; Cellitti, D. ; Pontarelli, S.
more authors

This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy

Published in:

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Date of Conference: