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Defect analysis and a new fault model for multi-port SRAMs

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4 Author(s)
P. Nagaraj ; Digital Test Eng., QUALCOMM CDMA Technols., San Diego, CA, USA ; S. Upadhyaya ; K. Zarrineh ; D. Adams

Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified

Published in:

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Date of Conference:

2001