Scheduled System Maintenance:
On May 6th, single article purchases and IEEE account management will be unavailable from 8:00 AM - 5:00 PM ET (12:00 - 21:00 UTC). We apologize for the inconvenience.
By Topic

Parallel testing of multi-port static random access memories for BIST

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Karimi, F. ; Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Lombardi, F.

Presents a built-in-self test (BIST) technique to implement the parallel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. In the proposed hardware scheme, address data and control sequences are generated using a BIST controller originally designed for a single port memory; a simple logic unit is also used to interface the signals for BIST to the memory ports. It is shown that the proposed BIST implementation is O(N log N), where N is the number of ports

Published in:

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Date of Conference:

2001