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Parallel testing of multi-port static random access memories for BIST

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2 Author(s)
Karimi, F. ; Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Lombardi, F.

Presents a built-in-self test (BIST) technique to implement the parallel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. In the proposed hardware scheme, address data and control sequences are generated using a BIST controller originally designed for a single port memory; a simple logic unit is also used to interface the signals for BIST to the memory ports. It is shown that the proposed BIST implementation is O(N log N), where N is the number of ports

Published in:

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

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