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Yield-reliability modeling for fault tolerant integrated circuits

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3 Author(s)
T. S. Barnett ; Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA ; A. D. Singh ; V. P. Nelson

An integrated yield-reliability model for defect tolerant integrated circuits is presented that allows one to estimate the yield following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures and defects causing infant mortality failures. The two-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter α, while known to play a key role in accurately determining wafer probe yields of defect tolerant chips, is shown for the first time. to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ significantly from calculations that ignore clustering

Published in:

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Date of Conference: