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High throughput low-density parity-check decoder architectures

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4 Author(s)
Yeo, E. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Pakzad, P. ; Nikolic, B. ; Anantharam, V.

Two decoding schedules and the corresponding serialized architectures for low-density parity-check (LDPC) decoders are presented. They are applied to codes with parity-check matrices generated either randomly or using geometric properties of elements in Galois fields. Both decoding schedules have low computational requirements. The original concurrent decoding schedule has a large storage requirement that is dependent on the total number of edges in the underlying bipartite graph, while a new, staggered decoding schedule which uses an approximation of the belief propagation, has a reduced memory requirement that is dependent only on the number of bits in the block. The performance of these decoding schedules is evaluated through simulations on a magnetic recording channel

Published in:

Global Telecommunications Conference, 2001. GLOBECOM '01. IEEE  (Volume:5 )

Date of Conference:

2001