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Noise optimization of an inductively degenerated CMOS low noise amplifier

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2 Author(s)
P. Andreani ; Dept. of Electroscience, Lund Univ., Sweden ; H. Sjoland

This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:48 ,  Issue: 9 )
IEEE RFIC Virtual Journal
IEEE RFID Virtual Journal