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Simple digital test approach for embedded charge-pump phase-locked loops

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2 Author(s)
M. J. Burbidge ; Centre for Microsyst. Eng., Lancaster Univ., UK ; A. M. Richardson

Techniques for a simple automated test approach for high performance fully embedded charge-pump phase-locked loops (CP-PLLs) are explained. The test approach is focused towards non-invasive high volume production testing of PLLs using digital only testers in conjunction with additional on-chip circuitry

Published in:

Electronics Letters  (Volume:37 ,  Issue: 22 )