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Adiabatic carry look-ahead adder with efficient power clock generator

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3 Author(s)
Mahmoodi-Meinnand, H. ; Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA ; Afzali-Kusha, A. ; Nourani, M.

The performance and characteristics of an adiabatic logic family are studied and compared with those of combinational and pipelined static CMOS counterparts. An 8 bit adiabatic carry look-ahead adder and its combinational and pipelined static CMOS counterparts are designed using a 0.6 μm CMOS technology. The performance of each circuit is studied in terms of the maximum frequency of operation, the minimum voltage of operation, the circuit energy consumption, and the switching noise generated by the circuit. Based on the simulation results, depending on the operating frequency, the adiabatic adder exhibits energy savings up to 87% compared with its combinational and pipelined static CMOS counterparts. It also exhibits a considerable reduction in switching noise, compared with its static CMOS counterparts. Practical issues in the design of power clock generators needed by adiabatic logic circuits are also explained. Synchronous and asynchronous power clock generators are designed and the more energy efficient circuit for the power clock generation is determined. The power clock generator exhibits a conversion efficiency of 77% at 10 MHz operating frequency

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:148 ,  Issue: 5 )