Evaluation and implementation of advanced electronic packaging techniques for reliable, cost-effective miniaturized space electronics

Implementing advanced electronic packaging schemes in space electronics design is a desirable, cost-effective way to leverage existing technologies derived from consumer electronics. Demands for faster, better, lighter, and cheaper products have led to many innovative designs in commercial electronics. However, directly using commercially available packaging techniques in space electronics could be extremely risky without careful reliability study and assessment. With many years of experience in developing high-reliability electronics, the Space Department of the Johns Hopkins University Applied Physics Laboratory (JHU/APL) started the process of evaluating, qualifying, and developing commercial advanced packaging techniques for space application with chip-onboard (COB) technology. With our in-house fabrication and coating process, we can improve existing commercial COB technology to survive and function through the entire space mission. We have focused investigations on advanced interconnect methods such as flip-chip technology and high-density printed wiring board implemented with blind and buried microvias.