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A memory efficient motion estimator for three step search block-matching algorithm

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1 Author(s)

This paper describes a memory efficient array architecture with data-rings for the 3-step hierarchical search block-matching algorithm (3SHS). With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify control scheme and reduce latency, respectively. In addition, we utilize the three-half-search-area scheme and circular addressing method to reduce external memory access and memory size, respectively. The results demonstrate that the array architecture with a memory efficient scheme requires a smaller memory size and low I/O bandwidth. It also provides a high normalized throughput solution for the 3SHS

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:47 ,  Issue: 3 )

Date of Publication:

Aug 2001

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