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A 1.0 Gb/s BiCMOS multi-channel optical interface transmitter and receiver chip set for high resolution digital displays

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5 Author(s)
Gunsang Lee ; Dept. of Electron. Eng., Korea Univ., Seoul, South Korea ; Yong Sub Kim ; Jae Hun Lee ; Doo Hwan CHoi
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A 1.0 Gb/s multi-channel optical interface transmitter (Tx) and receiver (Rx) chip set is presented. We propose a new high speed serial digital video I/O scheme for high resolution liquid crystal displays (LCD) operating up to the SXGA(1280*1024 pixels) grade. By using an optical fiber as a channel, it is possible to implement the optical interface with a low EMI, high skew-tolerance, and long transmission distance. All the analog front ends such as a laser driver in the Tx and a PD current detector in the Rx are fully integrated in the chip set. The interface chip set has a data recovery system with ±1 bit skew compensation and an encoder/decoder for DC balancing. With a single 2.5 V supply operating at 1.0 Gb/s, the power consumption of the Tx is 150 mW and that of the Rx is 230 mW, respectively. They were implemented in a 0.5 μm, 3-metal BiCMOS process and occupy an active area of 3170*3440 mm2, each

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Consumer Electronics, IEEE Transactions on  (Volume:47 ,  Issue: 3 )