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The UCSC Kestrel high performance SIMD processor: present and future

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3 Author(s)
Mesa-Martinez, F. ; Jack Baskin Sch. of Eng., California Univ., Santa Cruz, CA, USA ; Perlman, E. ; Hughey, R.

The UCSC Kestrel parallel processor is a single-board linear array processor with 512 8-bit processing elements. In the process of building the machine, the authors have touched nearly all aspects of computer engineering, from VLSI layout to board design and debugging, and from device drivers to new algorithm development. The programmable array is primarily designed for several core algorithms from computational biology, on which Kestrel can outperform a workstation by a factor of 20. They have also considered a variety of other algorithms, including graph coloring, computational chemistry and neural network evaluation

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Frontiers in Education Conference, 2001. 31st Annual  (Volume:3 )

Date of Conference: