By Topic

Simulation experiments of a high-performance RapidIO-based processing architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
J. Adams ; Rydal R&D Inc, PA, USA ; C. Katsinis ; W. Rosen ; D. Hecht
more authors

Describes the results of our simulation analysis of a high-performance processing architecture based on the RapidIO network protocol. RapidIO is a 10-Gb/s, low-latency packet-switched interconnect technology designed for processor-to-processor, processor-to-memory, and processor-to-peripheral interconnects. Two network topologies were simulated, a simple network consisting of an 8-port switch and eight processing nodes and a more extensive network consisting of five 8-port switches and 24 processing nodes. The results indicate that latencies as low as 92 ns for a remote 64-bit read request/response transaction may be achieved in an unloaded single-switch system. The effectiveness of various flow control mechanisms provided by the protocol are also explored, and when used in combination, a 10% increase in link utilization is achieved

Published in:

Network Computing and Applications, 2001. NCA 2001. IEEE International Symposium on

Date of Conference: