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In order to cater for communications users' needs in terms of high speed, high bandwidth and error free reception, researchers have focused their attention towards B-ISDN/ATM in recent years. Since the major efficiency of ATM networks depends on the ATM switching, we have focused our attention towards high throughput in an ATM switch architecture. The banyan switch architecture is taken for our study. We have simulated an 8×8 banyan architecture with the proposed scheme of using RS coder and decoder. The performance of the proposed architecture in terms of cell loss and average delay versus the cell arrival rate is presented.