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A low latency architecture for computing multiplicative inverses and divisions in GF(2m)

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3 Author(s)
A. V. Dinh ; Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask., Canada ; R. J. Bolton ; R. Mason

A low latency architecture to compute the multiplicative inverse and division in a finite field GF (2m) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers (2l) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:48 ,  Issue: 8 )