Design of a SOI fully integrated 1 V, 2.5 GHz front-end receiver

CMOS is a good candidate for an optimum single chip implementation of both the analog and digital blocks in wireless mobile transceivers. Concerning analog RF blocks, SOI CMOS offer advantages over CMOS bulk, such as reduced source/drain-substrate capacitance and elimination of body effect which are suited for low voltage supply, Furthermore, SOI offers the opportunity to use high resistivity substrates leading to high performances planar inductors and better substrate insulation. This paper describes the design of a fully integrated 2.5 GHz front-end receiver. including LNA and mixer, optimized for a 1 V supply in a 0.25 μm PD SOI. The simulation results show that SOI is very suitable for full integration of RF interfaces with low voltage and low power requirements