By Topic

0.15 /spl mu/m SOI DRAM technology incorporating sub-volt dynamic threshold devices for embedded mixed-signal & RF circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Goldman, D. ; Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA ; DeGregorio, K. ; Kim, C.S. ; Nielson, M.
more authors

This paper describes the DC and high frequency characteristics of a low-cost, 0.15 /spl mu/m PDSOI DRAM technology. A compact dynamic threshold (DT) device design in this process is found to be superior to both grounded body (GB) and floating body (FB) PD-SOI MOSFETs. This device achieves kink-free behavior, with gm=936 /spl mu/S/um, g/sub out/=36 /spl mu/S/um, Ion/Ioff=210 /spl mu/A/0.1 pA, S=67 mV/dec, and fmax=32 GHz at V/sub DD/=1 V. These DTMOS devices are excellent for sub-volt embedded baseband and IF circuits and sufficient for RF front-end circuits, thus enabling the combination of embedded DRAM, digital, analog and RF circuit cores in, ultra-low-power, low-cost SOCs.

Published in:

SOI Conference, 2001 IEEE International

Date of Conference:

1-4 Oct. 2001