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0.11 /spl mu/m fully-depleted SOI CMOS devices with 26 nm silicon layer fabricated by bulk compatible process

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6 Author(s)
Komatsu, H. ; LSI Technol. Dev. Div., Sony Corp., Atsugi, Japan ; Nakayama, H. ; Koyama, K. ; Matsumoto, K.
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A design for fully-depleted (FD) SOI CMOS devices is proposed. By optimizing halo/extension implantation and a thin CoSi/sub 2/ process, 0.11 /spl mu/m FD devices with a flat roll-off have been fabricated, even with a 26 nm thick Si layer . Using this "bulk compatible" technology, a good inverter switching speed of 14 ps (at V/sub dd/=1.2 V) has been achieved.

Published in:

SOI Conference, 2001 IEEE International

Date of Conference:

1-4 Oct. 2001

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