Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Instruction set simulators are indispensable tools for both the design of programmable architectures and software development. However, due to a constantly increasing processor complexity and the frequent demand for cycle-accurate models, such simulators have become defectively slow. The principle of compiled simulation addresses this shortcoming. Compiled simulators make use of a priori knowledge to accelerate simulation, with the highest efficiency achieved by employing static scheduling techniques. In the past, such statically scheduled simulators have only been implemented for specific DSP architectures. The approach presented discusses the application of static scheduling techniques to retargetable simulation tools based on the processor description language LISA. Principles and implementation issues are discussed, and results are presented for two selected processor architectures.