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On the design of modulo 2n±1 adders

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3 Author(s)
Efstathiou, C. ; Dept. of Informatics, TEI of Athens, Greece ; Vergos, H.T. ; Nikolos, D.

In this paper we present new architectures for the design of modulo 2n±1 adders, which are based on the use of the same design block. Our design block incorporates a parallel-prefix carry computation unit with a carry increment stage. VLSI implementations of the proposed architectures in a static CMOS technology reveal their superiority against all already known architectures when the area * time 2 product is used as a metric and n > 8

Published in:

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:1 )

Date of Conference:

2001