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Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers

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2 Author(s)
N. Tomabechi ; Hachinohe Inst. of Technol., Japan ; T. Ito

This paper presents a high-speed RSA encryption processor employing a highly parallel architecture based on the redundant binary number arithmetic and table-look-up, and also presents a defect-tolerance design suitable for the processor to solve the low yield problem. It is demonstrated that the gate delay through the critical path determining the operation speed of the processor is 1/60 that of the conventional processor. It is also demonstrated that the increase of chip size by introducing defect-tolerance is 6.4% and the increase of delay is minimized

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Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:1 )

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