By Topic

Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tomabechi, N. ; Hachinohe Inst. of Technol., Japan ; Ito, T.

This paper presents a high-speed RSA encryption processor employing a highly parallel architecture based on the redundant binary number arithmetic and table-look-up, and also presents a defect-tolerance design suitable for the processor to solve the low yield problem. It is demonstrated that the gate delay through the critical path determining the operation speed of the processor is 1/60 that of the conventional processor. It is also demonstrated that the increase of chip size by introducing defect-tolerance is 6.4% and the increase of delay is minimized

Published in:

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:1 )

Date of Conference:

2001