Referenced Items are not available for this document.
A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show the feasibility of the technique and the substantial reduction of the nonlinearity down to values lower then 1%
Published in:
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
(Volume:2
)
Date of Conference: 2001
- Page(s):
- 1001 - 1005 vol.2
- Meeting Date :
- 02 Sep 2001-05 Sep 2001
- Print ISBN:
- 0-7803-7057-0
- INSPEC Accession Number:
- 7184064
- Digital Object Identifier :
- 10.1109/ICECS.2001.957642
- Product Type:
- Conference Publications
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