By Topic

Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
Silvagni, A. ; Memory Product Group, STMicroclectronics, Milan, Italy ; Zanardi, S. ; Manstretta, A. ; Scotti, M.
more authors

This paper presents a family of 2 b/cell devices fabricated in 0.15 μm STI CMOS technology NOR-type flash memory. The device organization is based on a modular architecture that allows a very fast generation of all devices of the family from 64 Mbit to 256 Mbit having very similar performance. The modular architecture mainly concerns read path and high Voltage management aspects. A very realistic chip emulation of all devices is possible by using the 256 Mbit parent chip. The 256 Mbit device has 90 mm2 die size and it is composed of 256 1-Mbit sectors with hierarchical row and column decoding. Asynchronous access time with error correction is 120 ns for the 256 Mbit. Burst mode read at 50 and 66 MHz is also available

Published in:

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:2 )

Date of Conference: