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A code transformation-based methodology for improving I-cache performance

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4 Author(s)
Liveris, N. ; VLSI Design Lab, Patras Univ., Greece ; Zervas, N.D. ; Kakaroudas, A.P. ; Goutis, C.E.

This paper focuses on I-cache behaviour enhancement through the application of high-level code transformations. Specifically, a flow for the iterative application of the I-Cache performance optimizing transformations is proposed. The procedure of applying transformation is driven by a set of analytical equations, which receive parameters related to code and I-cache structure and predict the number of I-cache misses

Published in:

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:2 )

Date of Conference:

2001