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On placement and routing of wafer scale memory

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6 Author(s)
Li-An Sung ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Jiang, I.H.-R. ; Yoh-Wen Chang ; Jing-Yang Jou
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The progress of computer technology triggers the requirement of high speed and large volume memory. In modern manufacturing, a memory module is integrated by packaged memory chips on a printed circuit board. This paper proposes two architectures directly to integrate a memory module at the wafer level before packaging. This method can reduce the area, enhance the performance, and save the packaging cost. A polynomial time algorithm is presented to find the placement that minimizes the critical delay of the module. The routing is subsequently applied, and laser cutting technology is adopted to remove the unnecessary connections. Experimental results show that our approaches are very efficient and effective. A 64 M×128 bit module is completed in 348.38 second runtime and 4664 KB memory, and the delay is improved 88.67%

Published in:

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:2 )

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