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Formal verification of digital circuits by 3-valued simulation

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2 Author(s)
A. M. Wahba ; Mentor Graphics, Egypt ; E. J. Aas

A new technique for digital circuit verification is presented. The new technique is based on the 3-value simulator, 3 VS. Our motivation for utilizing 3 VS is the desire to bridge the gap between common industrial practice of verification through simulation, and the world of formal verification. A metric for verification coverage is defined, and it is shown to provide a lower bound of design confidence. 3 VS and OBDD-based formal verification are compared, and none of the methods is declared generally superior

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Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:2 )

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