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New test pattern generation units for NPSF oriented memory built-in self test

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4 Author(s)
Chrisarithopoulos, A. ; Adv. Silicon Solutions Div., Integrated Syst. Dev. S.A, Athens, Greece ; Haniotakis, T. ; Tsiatouhas, Y. ; Arapoyanni, A.

In this paper we present the design of deterministic test pattern generation (TPG) units which can be exploited in a built-in self-test (BIST) scheme for memory neighborhood pattern sensitive fault (NPSF) testing. The proposed TPG units generate the required Eulerian sequence of test patterns for memory type-1 NPSF testing

Published in:

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:2 )

Date of Conference:

2001