Referenced Items are not available for this document.
In this paper we present the design of deterministic test pattern generation (TPG) units which can be exploited in a built-in self-test (BIST) scheme for memory neighborhood pattern sensitive fault (NPSF) testing. The proposed TPG units generate the required Eulerian sequence of test patterns for memory type-1 NPSF testing
Published in:
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
(Volume:2
)
Date of Conference: 2001
- Page(s):
- 749 - 752 vol.2
- Meeting Date :
- 02 Sep 2001-05 Sep 2001
- Print ISBN:
- 0-7803-7057-0
- INSPEC Accession Number:
- 7176176
- Digital Object Identifier :
- 10.1109/ICECS.2001.957583
- Product Type:
- Conference Publications
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