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Design of low-power on-line reconfigurable datapaths using self-checking circuits

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3 Author(s)
A. P. Kakarountas ; Dept. of Electr. & Comput. Eng., Patras Univ., Greece ; V. Kokkinos ; C. E. Goutis

In this paper, a novel technique is illustrated to implement fault-tolerant circuits. On-line testing is used to detect errors and a reconfiguration technique is applied to by-pass the erroneous unit. The main characteristics of this technique are the reduced power dissipation compared to formal implementations and the minimum required time to perform the reconfiguration process. Application of this technique on FIRs is illustrated and a maximum of 40% is saved from the area required for integration, while 33% power reduction is achieved

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Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:3 )

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