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Low-power logic styles for full-adder circuits

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4 Author(s)
J. M. Quintana ; Centro Nacional de Microelectron., Instituto de Microelectron. de Sevilla, Seville, Spain ; M. J. Avedillo ; R. Jimenez ; E. Rodriguez-Villegas

This paper contributes to a better knowledge of the behaviour of conventional CMOS and CPL full-adder circuits when low voltage, low power or small power-delay products are of concern. It completes and overcomes limitations of previous studies as optimal power-delay curves, for CPL and CMOS full adders, have been constructed using an automatic sizing tool based on statistical optimization. Supply voltages of 3.3 V and 1.5 V have been considered. This study shows that full adders with minimum power consumption are accessible by using the conventional CMOS design style. As a counterpart, minimum delay full adders are obtained with CPL

Published in:

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:3 )

Date of Conference:

2001