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A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division

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4 Author(s)
Monteiro, F. ; SUPELEC, Metz Univ., France ; Dandache, A. ; M'sir, A. ; Lepley, B.

The CRC error detection is a very common function on telecommunication applications. The evolution towards increasing data rates requires more and more sophisticated implementations. In this paper, we present a method to implement the CRC function based on a pipeline structure for the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bits)

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Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on  (Volume:3 )

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