Referenced Items are not available for this document.
The CRC error detection is a very common function on telecommunication applications. The evolution towards increasing data rates requires more and more sophisticated implementations. In this paper, we present a method to implement the CRC function based on a pipeline structure for the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bits)
Published in:
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
(Volume:3
)
Date of Conference: 2001
- Page(s):
- 1231 - 1234 vol.3
- Meeting Date :
- 02 Sep 2001-05 Sep 2001
- Print ISBN:
- 0-7803-7057-0
- INSPEC Accession Number:
- 7189708
- Digital Object Identifier :
- 10.1109/ICECS.2001.957437
- Product Type:
- Conference Publications
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