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A multi-level block priority based instruction caching scheme for multimedia processors

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2 Author(s)
Jiyang Kang ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Wonyong Sung

A new instruction caching scheme that utilizes the block priority information is proposed mainly targeted for embedded multimedia processors. The block priority information is obtained by profiling application programs. The goal of this caching scheme is to keep more important code blocks longer using the block priority information, which programmers provide by analyzing the profiling results of multimedia applications. In addition to a new caching scheme, algorithms for determining the priority of each code block statically are also developed and their performances are evaluated using an H.263 video encoder. The experimental results show that the cache miss ratio can be reduced up to nearly a half of that of the normal least recently used (LRU) replacement scheme although the improvement depends on the cache size. The effects of varying cache size, associativity, and line size on the performance of proposed prioritization methods are also investigated. Moreover, the performance gain that can be achieved by employing more than two priority levels is also discussed

Published in:

Signal Processing Systems, 2001 IEEE Workshop on

Date of Conference: